1. Field of Art
The disclosure generally relates to statistical static timing analysis of electronic circuits and more specifically to analyzing delay variations and transition time variations in statistical static timing analysis of electronic circuits.
2. Description of the Related Art
Conventional ways of performing timing analysis of circuits include simulation based approaches. As the complexity of integrated circuits (ICs) grows, using simulation based approaches to verify timing constraints become impractical in view of long runtimes, low capacities, and incomplete analysis.
Another technique for performing timing analysis of circuits is static timing analysis (STA). Unlike the simulation based approaches, STA verifies timing by computing worst-case delays without enumerating all possible paths. Thus, STA can perform a thorough timing analysis for large ICs within a reasonable amount of time. Therefore, STA is the method of choice for verifying timing constraints for large ICs.
Design and fabrication of ICs involve complex physical and chemical processes which cause on-chip variation (OCV) of timing-related parameters. Typically, STA techniques model this OCV using global derating parameters used to determine delays to reflect OCV. Applying global derating parameters to each delay value often ignores context or location regarding the delay.
As the density of integrated circuits (ICs) increases, the dimension of the transistors becomes smaller. Furthermore there is a trend towards decreasing the operating voltage of circuits. As transistors become smaller and operating voltage continues dropping, local random variation becomes increasingly important for the performance of ICs. Various models are being developed to analyze local random variations and determine delay variations and transition time variations. However, conventional techniques are deficient in determining the impact of local random variations on the overall circuit.